1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory, and more particularly to a circuit for latching program data and at the same time programming data.
2. Description of the Related Art
It has been required to shorten the programming time in nonvolatile semiconductor memories such as ultraviolet erasable programmable read only memories (EPROMs) as the memory bit density increases. Therefore, the memories tend to be formed so as to have the page mode programming function of latching program data of several bytes and then simultaneously programming the data into a plurality of memory cells. In general, it is necessary to effect both the page mode programming operation and normal mode programming operation. Conventionally, the page mode and normal mode are selectively specified by a combination of input logic levels of four external input terminals (programming power supply voltage, PGM input terminal, chip enable CE terminal and output enable OE input terminal).
Such a prior art is disclosed in the following documents:
Takaaki Hagiwara, et al.
SESSION XIII: NONVOLATILE MEMORIES
"Page Mode Programming 1 Mb CMOS EPROM",
1985 IEEE International Solid-State Circuits Conference, ISSCC 85/THURSDAY, FEB. 14, 1985, pp. 174-175
The entire contents disclosed in the above documents are incorporated into this specification.
Part of the conventional EPROM is shown in FIG. 4 and the operation timings thereof is shown in FIG. 5. Data input/output terminal 41 is commonly connected to one end of data latch control transistors 431 to 434 of four bits via inverter circuit 42. The other ends of transistors 431 to 434 are respectively connected to input terminals of latch circuits 441 to 444. The output terminals of latch circuits 441 to 444 are respectively connected to the gates of programming or bit line load transistors 471 to 474 for programming via page mode programming control transistors 451 to 454 and inverter circuits 461 to 464. Transistors 471 to 474 are respectively connected to bit lines BL1 to BL4 which are in turn connected to a plurality of memory cells MC ... via column selection transistors (not shown). Further, the output terminal of inverter circuit 42 is connected to the input terminals of inverter circuits 461 to 464 via normal mode programming control transistors 481 to 484, respectively.
Four data latch controlling transistors 431 to 434 are selected according to a combination of low-order two bits A0 and A1 of address input bits A0 to An when signal OE is at a high level. As shown in FIG. 5, in the page mode signal PGM and CE are both set to a high level. At this time, input data D1 to D4 sequentially supplied to I/O terminal 41 are respectively latched by latch circuits 441 to 444 via data latch controlling transistors 431 to 434 which are sequentially turned on each time signal OE is set to a high level. When signal PGM is set to a low level, page mode programming transistors 451 to 454 are controlled so as to be turned on at the same time. Then, data in latch circuits 441 to 444 are supplied to load transistors 471 to 474 via inverters 461 to 464 and are thus written into the four-bit memory cells at the same time. Next, in the verify mode in which signal PGM is set at a high level and signals CE and OE are both set at a low level, the programmed data is read out.
In the programming operation of the normal mode, one of normal mode programming control transistors 481 to 484 is selected according to address input bits A0 and A1, and input data is programmed via the selected load transistor.
As described above, three signals PGM, CE and OE can be variously combined to selectively set various modes of operations of the normal mode programming, page mode programming, programming inhibition, verify, latching of page mode programming data and the like.
In a case where PGM signal is omitted and only the remaining signals CE and OE are used, the circuit of FIG. 4 cannot be used. In order to solve the problem, the following method can be considered. That is, data may be latched in a short low-level period (T1) of signal CE, and the latched data may be programmed or written in a long low-level period (T2) of CE signal. In this case, signal OE is kept at a high level in the page mode programming operation, and is set to a low level for each data output. Further, in this case, when it is determined by use of a timer that a preset period of time (long low-level period of signal CE) has elapsed after signal CE was set to a low level in the normal mode programming operation, data is started to be programmed.
However, time loss occurs before the beginning of programming in the normal mode programming operation effected by use of the timer, and necessary programming time becomes longer. In other words, when it is desired to control the page mode programming and normal mode programming operations according to two control signals, the programming time in the normal programming operation will become longer.